Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families

M. Ahmadi, K. Raahemifar
2000 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
The delay fault testing in logic circuits is studied. It is shown that by detecting delayed time response in a transistor circuit, two types of faults are detected: 1) faults which cause delayed transitions at the output node due to some open defects and 2) faults which cause an intermediate voltage level at the output node. A test circuit is presented which enables the concurrent detection of delay faults. The proposed delay fault testing circuit does not substantially degrade the speed of the
more » ... circuit under test (CUT). Simulation results show that this technique fits any design style. Index Terms-Concurrent testing, delay fault and stuck open fault testing, design for testability, fully testable CMOS circuit, VLSI testing. . His research interests include simulation algorithms for mixed analog-digital circuits, design and testing of mixed analog/digital circuits, and developing computer-aided design tools. Majid Ahmadi (S'75-M'77-SM'84) received the B.Sc. degree in engineering from Arya Mehr University in Tehran, Iran, and the Ph.D. degree from
doi:10.1109/82.885134 fatcat:erlhh6kkmbaanlvljxhhhsgtki