Pass transistor logic and complementary pass-transistor logic (CPL) are becoming increasingly important in the design of a speci® c class of digital integrated circuits owing to their speed and power e ciency as compared with conventional CMOS logic. In this paper, a simple and very accurate technique for the timing analysis of gates that involve pass transistor logic is presented. This investigation oOE ers for the ® rst time the possibility of simulating pass transistor and CPL gates by

more »

... ioning the behaviour of complex structures into well de® ned subcircuits whose interaction is studied separately. Using the proposed analysis, which is validated by results for two submicron technologies, most pass-transistor logic styles can be modelled e ciently. Consequently, a signi® cant speed advantage can be gained compared with simulation tools that employ numerical methods such as SPICE.