A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
Performance of Graceful Degradation for Cache Faults
2007
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchitectural techniques to make processor components resilient to hard faults will become increasingly important. This paper considers defects in cache memory and studies their impact on program performance using a fault degradable cache model. We first describe how defects at the circuit level in cache manifest themselves
doi:10.1109/isvlsi.2007.81
dblp:conf/isvlsi/LeeCC07
fatcat:5qkwz6wwkzesdnkivg7m3zvb44