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A formal method to improve SystemVerilog functional coverage
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Improving functional coverage efficiently in a verification environment based on constrained random simulation could be a difficult task, since some design states are hard to be reached by random input patterns. On the other hand, manually crafting direct test patterns may be time consuming. In this paper, a functional test pattern generation (FTPG) framework is proposed to automatically produce deterministic test patterns for complete coverage. The framework is based on the functional coveragedoi:10.1109/hldvt.2012.6418243 dblp:conf/hldvt/ChengYJ12 fatcat:yb337hr7vzdjbibwcpoxle63e4