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Instruction set extensions for photonic synchronous coalesced accesses
2013
2013 IEEE High Performance Extreme Computing Conference (HPEC)
Microprocessors have evolved over the last fortyplus years from purely sequential single operation machines, to pipelined super-scalar, to threaded and SIMD, and finally to multi-core and massive multi-core/thread machines. Despite these advances, the conceptual model programmers use to program them is still that of a single threaded register file bound math unit that can only be loosely synchronized with other such processors. This lack of explicit synchrony, caused by limitations of metal
doi:10.1109/hpec.2013.6670326
dblp:conf/hpec/KeltcherWH13
fatcat:y7fki3y375fsvpdumbgldwy4ze