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VLSI design (Print)
Networks-on-Chip (NoCs) are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well established CAD deployment tools to tackle the large amount of available degrees of freedom, starting from the choice of a network topology. "Silicon-aware" optimization tools are now emerging in literature; they select an NoC topology taking into account thedoi:10.1155/2007/50285 fatcat:iynxzgm44jcahkfmyqpahfww3y