Rationale for a 3D heterogeneous multi-core processor

Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon
2013 2013 IEEE 31st International Conference on Computer Design (ICCD)  
Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior. This paper makes a case for implementing a heterogeneous multi-core processor via 3D die stacking. The case is
more » ... from three angles: product strategy, architecture, and physical design. Product strategy: Die stacking enables plug-andplay composition of heterogeneous processors from homogeneous designs, a more efficient product customization strategy than fabricating dedicated 2D heterogeneous processors. Architecture: Frequent thread migrations substantially increase the benefits of microarchitectural diversity, but only if migration can be done with very low overhead. Thus, fast transfer of architectural state and uninterrupted access to accumulated microarchitectural state are essential. Physical design: Exchanging/referencing state between cores with low latency requires many new wires that must also be as short as possible, introducing intense physical design pressures and tradeoffs in a 2D layout that are diminished in a 3D layout. We are currently researching applications and fabricating prototypes of "H3", a 3D heterogeneous multi-core processor. H3's salient features include: two core types for optimizing latency and energy; a power management unit (PMU) that schedules migrations; fast thread migration (FTM) and cachecore decoupling (CCD) via face-to-face, microbump based buses; face-to-back, through-silicon-via (TSV) based buses connecting the core stacks to stacked L2 DRAM cache. The H3 project spans applications, processor architecture, circuits, logic and physical design/verification, design automation, fabrication and post-silicon validation. There are close interactions among all elements, both in terms of executing the project and in empirically justifying 3D-enabled heterogeneity. Thus, H3 is illustrative of the multi-disciplinary mission of this conference proceedings, the International Conference on Computer Design. • Product strategy -plug-and-play composition of many HMPs from a small portfolio of single-core-type chips.
doi:10.1109/iccd.2013.6657038 dblp:conf/iccd/RotenbergDFZWCTLDF13 fatcat:fufwfjcjvvhirpruhjlxr32see