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Revisiting Cache Block Superloading
[chapter]
2009
Lecture Notes in Computer Science
Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application characteristics. This approach to bridging the processor/memory performance gap has been studied before, but mostly via trace-driven simulation, looking only at L1 caches. Given changes in hardware/software technology, we revisit the general approach: we propose a transparent, phase-adaptive, low-complexity mechanism for L2
doi:10.1007/978-3-540-92990-1_25
fatcat:ehu4b3qejbdu7lt5j5rxaki2xm