A formal technique for hardware interface design

A. Baganne, J.L. Philippe, E. Martin
Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97  
In this paper, we consider the problem of hardware interface design in a codesign approach for real-time digital signal processing (DSP) applications. We refer to the hardware component as ASICS (Applied Specific Integrated Circuits) and the software component as processors. We describe a formal technique to communication synthesis starting from hardware I/O transfer sequences computed by a high level synthesis tool, like GAUT. The original nature of our work is the fact that a communication
more » ... erface is generated at the same time as the hardware module which leads to better performance and optimization and ensures communication data coherency. Our design strategy starts from the hardware I/O transfer sequences computed by GAUT. It incorporates some interface specification (I/O transfer order, timing constraints) obtained by any cosynthesis tool. The proposed allocation procedure of necessary storage components needed for data communication between hardware-software components assigns for each I/O data a time interval at which its transfer could occur. As an illustration, we present a mixed implementation of the GMDF alpha algorithm, an adaptive filter well suited to acoustic echo cancellation, on both ASIC and TS320C40 DSP.
doi:10.1109/iscas.1997.621435 fatcat:kptqddd6rfgz7emi2znpfjduju