Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

Stefan Biereigel, Szymon Kulis, Paulo Moreira, Alexander Kölpin, Paul Leroux, Jeffrey Prinzie
2021 Electronics  
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.52/mg as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a
more » ... ghly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40–320 or at data rates from 40Mbps–320Mbps and displays a jitter performance of 520 with a power dissipation of only 11 and an FOM of −235 .
doi:10.3390/electronics10222741 fatcat:5wrqurtw4rchhad4id5obr5euq