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Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While existing model checking based approaches have proposed several promising ideas for efficient test generation, many challenges remain in applying them to realistic pipelined processors. The time and resources required for test generation using existing model checking based techniques can be extremely large. This paperdoi:10.1109/date.2006.244078 dblp:conf/date/KooM06 fatcat:gb2ncf3zpfgyhcgivdto6cjxhq