A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf
.
Power Reduction Techniques In Vlsi
2018
Zenodo
The paper investigates different level of techniques used for power reduction in VLSI. Before, most of the researches were oriented towards bringing about high speed and miniaturization. At present, because of the increasing trend of compact devices, the requirement for low power consuming circuits have also increased. This necessitates the need to align the research for reducing power dissipation in VLSI circuits. In the given paper we will briefly discuss about the different types of power
doi:10.5281/zenodo.1200290
fatcat:t46h3oo4urcqtaxjmwmbrm6es4