SLIP

Patrick Groeneveld, Lou Scheffer, Dirk Stroobandt
2010 Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction - SLIP '10  
Panel Summary Founded in 1999, the ACM SLIP Workshop is now in its 12th year. The 2010 SLIP Panel session will highlight perspectives from three individuals who have had great influence on the course of SLIP, and provide an opportunity for lively discussion by workshop attendees of prospects for the next 10 years of SLIP. This panel summary records preliminary thoughts of the panelists on two starting questions. Q1: How do you see the scope, role, etc. of SLIP having changed since 1999? Patrick
more » ... Groeneveld. My job at Magma forces a low-level perspective on interconnect planning in an ASIC design flow. The chip needs to work, and timing and DRC must be closed by any means. Therefore, my interest in system-level interconnect prediction is primarily driven by the correlation accuracy as compared to the actual physical routing wires. Miscorrelation leads to routing and timing closure issues in the back-end. In fact, there is no meaningful application of system-level interconnect prediction without this correlation. Since the first SLIP in 1999, the core problem statement has not changed much. We must admit that SLIP tool applicability has been rather marginal. SLIP is the project of a small community, and the practical use is constrained to several basic technology-level interconnect planning issues (e.g., how many metal layers and what should be their pitch?). Since 3-D chips do allow the user to control the structure of the interconnect layers, I would expect more interest in the coming years. ACM 978-1-4503-0037-7/10/06. 10 years ago, we were mainly concerned with wire length and statistical properties of a graph theoretical interconect model combined with a simple model of the physical characteristics of interconnect. The main correlation issue was between the detailed router and the interconnect estimates. Now performance and power are critical, in addition to wireability. This makes SLIP much harder, since high performance interconnect takes more area and more power. A design, at low performance, might be wired with all minimum size wires. For the exact same design, with an unchanged interconnect graph and Rent descriptors, as the performance target is raised, more and more wires will need to be promoted to higher performance layers or technologies, and the wiring space will grow. Also, depending on the design, anywhere from just a few wires, to all of them, will need to be promoted. This shows interconnect prediction must take performance, function, and the timing details of the design into account. Also, 10 years ago, there was very little interaction between coding of data and the design of interconnect, at least for the short range connections found on chips. Now this is increasingly important, particularly since crosstalk can account for a large percentage of delay. Dirk Stroobandt. My position statement: "Forget about individualism, it's all about socialism". In a decade of SLIP research there has been a strong dichotomy between the fundamental statistical nature of Rent's rule based estimates and the quest for individual wire performance measures. On the one hand, the very nature of Rent's rule (as a scaling argument) naturally leads to a global model of interconnection lengths. All wires are "connected" (pun intended), so that classifying one wire automatically restricts the classification of the other wires. The force-directed placement model illustrates this very well, as all gates are modeled as being connected by springs where you would have connections. Pushing two gates together releases the force in one spring, but increases it in other springs connected to that particular gate. This global view on the interconnect problem is also very well reflected by the Donath-based interconnection length prediction models and (especially) their extensions of the mid-1990's. The global interconnection length model was very well suited to the CAD problems of that time, where placement was based on a global estimate (and optimization) of total wire length, and routing was mainly based on congestion maps which are already a bit more localized but still global 67
doi:10.1145/1811100.1811116 dblp:conf/slip/GroeneveldSS10 fatcat:wj535b7m3nhwbkm6tc4kbxq4cm