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Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)
We describe a methodology for verifying system-on-chip designs. In our methodology, the problem of verifying system-on-chip designs is decomposed into three tasks. First, we verify, once and for all, the standard bus interconnecting IP Cores in the system . The next task is to verify the glue logic, which connects the IP Cores to the buses. Finally, using the verified bus protocols and the IP core designs, the complete system is verified. To illustrate our methodology, we verify the PCI Localdoi:10.1109/asic.1999.806467 fatcat:e7i77u3yuzfhjcmvadear5mi74