Recent developments in Si based tunnel diode technologies have made the realization of circuits incorporating both t,unnel diodes and transistors feasible (1-21. hlemory circuits incorporating low current dencity double barrier resonant tunneling diodes (DBRTDs) [3] have been demonstrated with fewer transistors and lower power dissipation than conventional CMOS SRAM or DR.411 circuitry. High current density DBRTDs, in contrast, have been shown to improve the speed and power of logic circuit.ry

more »

... uch as multiplexers 141 and analog-to-digital converters IS]. However, such technology will never reach mainstream CMOS or SiGe HBT technology unless a suitable Si-based negative differential resistance (NDR) device can be developed. A recent study by the authon presented the dettign of an n-on-p Si RITD layer with a peak-t,o-valley current ratio (PVCR) of 2.15 at a current density of 3 kA/cm2 which was grown by molecular beam epitaxy (MBE) 161. The schematic diagram of thk structure, which is used as the base sample in the present study, is shown in Fig. 1 , and the current-voltage (I-V) characteristiol of this layer are shown in Fig. 2 . Follow-up st.udies on this structure investigated additional tunnel barrier thicknes.ses of 4 nm, 8 run, and 10 nm. In all samples, room temperature NDR was observed comparable to that of the baseline 6 nm RITD. Fig. 3 illustrates the exponential dependence of the current density on the tunnel barrier thickness. This figure clearly shows that simple adjustments to the tunnel barrier thickness can be made to tailor the performance for a particular circuit application. However, growth of a complimentary gon-n tunnel diode is problematic due to Sb segregation through the intrinsic tunneling spacer. This would result in unintentional incorporation and increased compensation by the segregated Sb and hence lower PVCR. A utudy, which will be published elsewhere, details a growth technique whi& overcomes these difficulties. The solution is to control the Sb segregation by employing multiple substrate temperatures during MBE growth. The Sb H o p i n g plane is first deposited at 320°C. This will minimize the degree of segregation, and ensure that a large percentage of dopants incorporate into the lattice during the growth of the Sb &doping plane. The Sb flux will then terminate. and a fixed length of Si (referred to as L1) will b e grown at 320°C. The Si flux will then be terminated for a stop growth. At this point, the substrate temperature is then elevated for the remainder of the sample growth, including the deposition of the B Moping plane. Thus, rather than dropping the substrat.e temperature to suppress Sb segregation, the substrate temperature is elevated to promote segregation while simultaneously minimizing Sb incorporation. Fig. 6 illustrates this process for the case whjch yielded the best results, an L1 length of 5 nm, and a length of 3 nm after the stop growth and prior to the B &doping plane. Fig. 5 shows the I-V characteristics of the pon-n sample annealed at 575"C, 1 min. Note that the resulting PVCR of 2.1 and peak current density of 1.1 kA/cm2 are comparable to that of the n-on-p 6 nm RITD shown in Fig. 1 . Following the success of the complementary p-on-n growth strategy, it was now possible to dem0nstrat.e the integration of two tunnel diodes in a single growth. The basic flow and design presented here follow that of 111-V MTDs 171, presenting a symmetric pnp FUTD structure. The motivation for developing this structure was to mimic the I-V characteristic of 111-V WDs which have NDR regions under forward and reverSe bias. A Si-based structure with these properties would facilitate t,he development of a Goto-type memory cell (81. Ideally, the PVCR and peak current density of the forward and reverse NDR regions should be nearly identical if the structure grown is symmetrical. Fig. 6 shows the ideal structure which in essence consists of two 6 nm Si RITD layers. As Fig. 6 illustrates, the growth of this sample combines the growth procedures for the devices shown in Figs. 1 and 4. Fig. 7 shows the EV characterist.irs resulting from a 6OO"C, 1 min anneal for the pnp RITD. Note that when a forward bias is applied, the device nearer the surface (the top diode) will be under forward bias, and when a reverse bias is applied with respect to the layers, the device nearer the sulwtrat,e (the bottom diode) will be under forward bias. As theorized. NDR is clearly present in the forward and reverse direct.ions with a PVCR of 1.67 for the top diode and 1.37 for the bottom diode. An asymmetry is clearly present in the layer as the current density of the bottom diode (5.7 kA/cm2) is over doubie that of the top diode (2.6 kA/cm2). With grm-th modifications it should be possible to achieve a symmetric I-V characteiist.ic. This simple example of integration has demonstrated that it is relatively straightforward to combine two growth templates in a single epitaxial run. An obvious extension to this study would be the growth of a Si/SiGe heterojunction bipolar bramistor with a tunnel diode placed on the emitter for high frequency mixed signal applications. Relatively few changes to the growth template would be required to make the structure work. In conclusion, a variety of Si-bawd tunnel diode structures configured to meet the needs of a CMOS environment have k e n demonstrated. REFERENCES [I] S. , 'Room temperature operation of epitaxially y w n Si/SiCe/Si resonant interband tunneling diodas,' Appl.