Notch reduction in silicon on insulator (SOI) structures using a time division multiplex etch processes

Shouliang Lai, Sunil Srinivasan, Russell J. Westerman, Dave Johnson, John J. Nolan, Mary-Ann Maher, Harold D. Stewart
2005 Micromachining and Microfabrication Process Technology X  
Silicon on Insulator (SOI) substrates are being increasingly used in MEMS applications, with the insulating layers serving as etch stop/sacrificial layers and/or device function layers. Apart from the conventional etching requirements including high etch rate, high selectivity and smooth sidewall, satisfactory etching of SOI wafers requires no notching at the silicon/insulator interface. Notching results from electrical charging effects and the consequent bending of the trajectories of arriving
more » ... ctories of arriving ions into feature sidewall. Notching is also aggravated due to the aspect ratio dependent etching effect. At Unaxis USA, we have developed a proprietary technique to alleviate the problem of notching. This technique is integrated into Unaxis' advanced DSE TM III silicon etching technology. A conventional time division multiplexed process is used during the bulk etch process while a proprietary finish etch process is used to eliminate notching. The transition between the bulk etch process and finish etch process is enabled using an advanced optical emission end point technique. The finish etch process is characterized and notch performance is measured as a function of overetch percentage and feature aspect ratio. Using this technique, notching is completely eliminated in aspect ratios of 8:1 and lower and reduced to less than 200 nm for aspect ratios up to 25:1.
doi:10.1117/12.582764 fatcat:7jrhs7a4wbdp5naww6maxs5qti