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PERFORMANCE ANALYSIS OF POWER GATING TECHNIQUES IN 4-BIT SISO SHIFT REGISTER CIRCUITS
2017
Journal of Engineering Science and Technology
The last few years have witnessed great deal of research activities in the area of reversible logic; the intrinsic functionality to reduce the power dissipation that has been the main requirement in the low power digital circuit design has garnered more attraction to this field. In this paper various power gating techniques for power minimization in adder and 4 bit serial in serial out (SISO) shift register circuits is proposed. The work also analyze various leakage reduction approaches such as
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