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Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload
2005
Journal of Parallel and Distributed Computing
In this work, we characterized the memory performance-and in particular the impact of coherence overhead and process migration-of a shared-bus shared-memory multiprocessor running a DSS workload. When the number of processors is increased in order to achieve higher computational power, the bus becomes a major bottleneck of such architecture. We evaluated solutions that can greatly reduce that bottleneck. An area where this kind of optimization is important regards data base systems. For this
doi:10.1016/j.jpdc.2004.10.003
fatcat:6bc2psq4ubcrpm2b637bnm64ni