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We present Outrider, an architecture for throughput-oriented processors that provides memory latency tolerance to improve performance on highly threaded workloads. Outrider enables a single thread of execution to be presented to the architecture as multiple decoupled instruction streams that separate memory-accessing and memory-consuming instructions. The key insight is that by decoupling the instruction streams, the processor pipeline can tolerate memory latency in a way similar todoi:10.1145/2000064.2000079 dblp:conf/isca/CragoP11 fatcat:w56fto3w4vgoxamabvgcrkb2z4