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Linear sum codes (LSC's) form a class of error control codes designed to provide on-chip error correction to semiconductor random access memories. They use the natural addressing scheme found on RAM's to form and access codewords with a minimum of overhead. In this paper, we formally define linear sum codes and examine some of their characteristics. Specifically, we examine their minimum distance characteristics, their error correcting capabilities, and the complexity involved in theirdoi:10.1109/12.2254 fatcat:tkvihzszk5aorfj2m5geevdzgi