Linear sum codes for random access memories

T. Fuja, C. Heegard, R. Goodman
1988 IEEE transactions on computers  
Linear sum codes (LSC's) form a class of error control codes designed to provide on-chip error correction to semiconductor random access memories. They use the natural addressing scheme found on RAM's to form and access codewords with a minimum of overhead. In this paper, we formally define linear sum codes and examine some of their characteristics. Specifically, we examine their minimum distance characteristics, their error correcting capabilities, and the complexity involved in their
more » ... d in their implementation. In addition, we look closely at an easily implemented class of single, double, and triple-error correcting linear sum codes.
doi:10.1109/12.2254 fatcat:tkvihzszk5aorfj2m5geevdzgi