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An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers
2014
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14
High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level (RTL) specifications. The highthroughput computation raises a high data demand. To prevent data accesses from being the bottleneck, on-chip memories are used as data reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to
doi:10.1145/2593069.2593090
dblp:conf/dac/CongLXZ14
fatcat:7yiii4ix7vh3vfdhryt7edjbz4