From the bitstream to the netlist

Jean-Baptiste Note, Éric Rannaud
2008 Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays - FPGA '08  
We present an in-depth analysis of the Xilinx bitstream format. The information gathered in this paper allows bitstream compilation and decompilation. While not actually compromising current bitstream security, the easiness of the decompilation process should raise awareness about bitstream security issues. Available documentation from Xilinx and some custom assumptions about the bitstream format are presented and analyzed, so as to first gather a database mapping bitstream data to its related
more » ... ata to its related netlist elements, thanks to a suitable algorithm applied to a well-chosen bitstream. This database is then used as input to an efficient program which can compile a bitstream from a low-level textual description or conversely decompile a bitstream to the same textual description for any subsequent input. The whole process of database gathering and the decompilation of the bitstream format for a particular chip runs at about the speed of bitgen compilation. The sole process of compiling/decompiling a bitstream from/to its associated textual description runs two orders of magnitude faster.
doi:10.1145/1344671.1344729 dblp:conf/fpga/NoteR08 fatcat:6b6ward5j5aotdd7y4vgg23h54