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Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not exploit common instruction-level parallelism (ILP) features, consequently exhibiting large errors when used to model current systems. A few newer simulators model current ILP processors in detail, but we find them to be about ten times slower. We propose a new simulation technique, based on a novel adaptation of directdoi:10.1109/hpca.1999.744317 dblp:conf/hpca/DurbhakulaPA99 fatcat:6xuxsfuqy5azvizlwfhqvckoqy