Improving the accuracy vs. speed tradeoff for simulating shared-memory multiprocessors with ILP processors

M. Durbhakula, V.S. Pai, S. Adve
1999 Proceedings Fifth International Symposium on High-Performance Computer Architecture  
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not exploit common instruction-level parallelism (ILP) features, consequently exhibiting large errors when used to model current systems. A few newer simulators model current ILP processors in detail, but we find them to be about ten times slower. We propose a new simulation technique, based on a novel adaptation of direct
more » ... aptation of direct execution, that alleviates this accuracy vs. speed tradeoff. We compare the speed and accuracy of our new simulator, DirectRSIM, with three other simulators -RSIM (a detailed simulator for multiprocessors with ILP processors) and two representative simple-processor based simulators. Compared to RSIM, on average, DirectRSIM is 3.6 times faster and exhibits a relative error of only 1.3% in total execution time. Compared to the simple-processor based simulators, DirectRSIM is far superior in accuracy, and yet is only 2.7 times slower. ¥ DirectRSIM, on average, is 3.6X faster than RSIM with an error in execution time of only 1.3% (range of -3.9% to 2.2%). ¥ Simple-processor based simulators remain an average of 2.7X faster than DirectRSIM. However, this addi-
doi:10.1109/hpca.1999.744317 dblp:conf/hpca/DurbhakulaPA99 fatcat:6xuxsfuqy5azvizlwfhqvckoqy