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In this paper, we address the problem of VLSI floorplanning with considering boundary constraints. The problem is practical and crucial in physical design since architects decide to arrange some I/O involved modules along the chip boundary to minimize both chip area and off-chip connections. By using a new representation called Generalized Polish Expression, we propose an efficient algorithm to handle the boundary constraints on non-slicing floorplans. In addition, a new fixing heuristic baseddoi:10.1145/1119772.1119838 dblp:conf/aspdac/ChenLW03 fatcat:opzvif7ugzdfnpvi34lnawcqma