Non-slicing floorplans with boundary constraints using generalized polish expression

De-Sheng Chen, Chang-Tzu Lin, Yi-Wen Wang
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
In this paper, we address the problem of VLSI floorplanning with considering boundary constraints. The problem is practical and crucial in physical design since architects decide to arrange some I/O involved modules along the chip boundary to minimize both chip area and off-chip connections. By using a new representation called Generalized Polish Expression, we propose an efficient algorithm to handle the boundary constraints on non-slicing floorplans. In addition, a new fixing heuristic based
more » ... ng heuristic based on modular similarity is also presented to effectively fix the generated infeasible floorplans during the process. The experimental result is good in commonly used MCNC benchmark circuits.
doi:10.1145/1119772.1119838 dblp:conf/aspdac/ChenLW03 fatcat:opzvif7ugzdfnpvi34lnawcqma