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An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
2011
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)
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This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-Encoded Dual-Rail (LEDR) protocol. FPDR protocol is employed to achieve small area for logic blocks, while LEDR protocol is employed to obtain high bit rate and low power for data transfer. Each logic block consists of LEDR-FPDR protocol converter, FPDR-LEDR protocol converter and two pipelined FPDR LUTs that alternately operate. The proposed FPGA is designed using the
doi:10.1109/aspdac.2011.5722311
dblp:conf/aspdac/KomatsuIHK11
fatcat:ttheydymdnfrhlygh2egbetyda