ULSI architectures for artificial neural networks

U. Ruckert
<span title="">2002</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/gvjkwgwwvnakpbfssxpqjozbqm" style="color: black;">IEEE Micro</a> </i> &nbsp;
The ongoing revolutionary progress of microelectronics is the driving force behind the constant development of new technical products that have markedly improved functionality and higher performance, yet at a lower cost. We expect this trend to continue beyond the year 2015. The challenge lies in mastering the resulting design complexity and achieving economic viability for integrated systems with more than 100 million devices per square centimeter. This requires system concepts that both
more &raquo; ... t the possibilities of semiconductor technology and reduce the design and test complexity. Because of their highly regular, modular structure, information processing parallelism, inherent fault tolerance, learning ability, and environmental adaptability, artificial neural networks (ANNs) offer an attractive alternate approach for ultra-largescale-integration (ULSI) systems. ANNs offer a variety of techniques for use in resource-efficient information processing architectures, and, in particular, for cognitive systems. The three approaches we examined are modelspecific integrated circuits for neural associative memories, self-organizing feature maps, and local cluster neural networks. With structure sizes smaller than 0.1 micron, semiconductor technology starts falling below the level of biological structures forming the brain. However, the brain efficiently uses all three dimensions, whereas microelectronics can use only the two physical dimensions of the silicon die surface. Nevertheless, taking an area of one square millimeter-roughly the square dimension of a Purkinje cell (a type of neuron) in the cerebellar cortex, shown in Figure 1a we can use 0.18-micron CMOS technology to implement a digital artificial neuron ( Figure 1b) with 170,000 8-bit weights (synapses) and an 8-bit microprocessor as a neural processing unit (Figure 1c) . Weights are the practical implementation (in hardware, software, theory) of (biological) synapses (contacts between nerve cells). Two approaches exist for supporting ANNs in parallel computing architectures: generalpurpose neurocomputers for emulating a wide range of neural network models, and specialpurpose ULSI systems dedicated to a specific neural network model. General-purpose neurocomputers offer a high degree of observability of the inner workings of neural algorithms as well as flexibility. Special-purpose ULSI designs offer resource-efficient speed, size, and power consumption. Progress continues in both approaches, and researchers have realized many different architectures in working hardware. There exists a variety of architectures within these two approaches. This is necessary to address the difficulty in determining the best way to perform ANN
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