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A way-halting cache for low-energy high-performance systems
Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04
Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. The lookup in the halt tag array is done in parallel with, and is no slower than, the set-indexdoi:10.1145/1013235.1013272 dblp:conf/islped/ZhangVYN04 fatcat:wdv4klj4fbfl5futtz7ipu5yqq