Sequential equivalence checking

A. Mathur, M. Fujita, M. Balakrishnan, R. Mitra
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
Traditional equivalence checkers used for RTL-to-gate-level equivalence rely on the exact matching of state points to reduce the problem of proving equivalence between the two models to that of proving equivalence between the next state functions of the corresponding state points and the functions at corresponding outputs. They are hence classified as combinational equivalence checkers.
doi:10.1109/vlsid.2006.145 dblp:conf/vlsid/MathurFBM06 fatcat:7j3oo7uynvb5hbc7culkmsvfmu