SmartScan - Hierarchical test compression for pin-limited low power designs

K. Chakravadhanula, V. Chickermane, D. Pearl, A. Garg, R. Khurana, S. Mukherjee, P. Nagaraj
2013 2013 IEEE International Test Conference (ITC)  
IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that
more » ... igh quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.
doi:10.1109/test.2013.6651897 dblp:conf/itc/ChakravadhanulaCPGKMN13 fatcat:qcvljrq26jexzb3jeq7s7aus6i