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A distributed interleaving scheme for efficient access to WideIO DRAM memory
2012
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12
Achieving the main memory (DRAM) required bandwidth at acceptable power levels for current and future applications is a major challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM memories promise to provide a significant boost in bandwidth at low power levels by exploiting multiple channels and wide data interfaces. In this paper, we address the problem of efficiently exploiting the multiple channels provided by standard (JEDEC's
doi:10.1145/2380445.2380467
dblp:conf/codes/SeiculescuBM12
fatcat:5czvs4lzjff63gw4fscr4i4cxy