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Design Of High Performance Reconfigurable Routers Using Fpga
International Journal of Information Engineering and Electronic Business
Abstrsact -Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce networkdoi:10.5815/ijieeb.2012.04.07 fatcat:dtpkuu3vlfg7vo5orf4yityrdi