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In today's VLSI technology nodes, interconnect delay plays an important part in deciding the performance of the chip designs. Various methods are introduced at the level of placement and routing to address this problem. To address this problem at the level of global routing, net weighting methods are being explored in the industry and academia. We investigate four methods for weighting the critical nets during performance driven global routing. This paper presents a comparative study conducteddoi:10.35940/ijrte.b1212.0782s319 fatcat:gcur6iwn5rgrfjxdpvnctyhkxu