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Trading cache hit rate for memory performance
2014
Proceedings of the 23rd international conference on Parallel architectures and compilation - PACT '14
Most of the prior compiler based data locality optimization works target exclusively cache locality optimization, and row-buffer locality in DRAM banks received much less attention. In particular, to the best of our knowledge, there is no single compiler based approach that can improve row-buffer locality in executing irregular applications. This presents a critical problem considering the fact that executing irregular applications in a power and performance efficient manner will be a key
doi:10.1145/2628071.2628082
dblp:conf/IEEEpact/DingKGJDY14
fatcat:a7j3vxei3bas3bbmasntq2bcua