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This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-duration profiles, and can be used to derive a noise susceptibility metric for the noise robustness of logic gates. Analytical methods -based upon calibration runs in circuit simulators -to determine noise susceptibility in the presence of variations in process, design, and environmental parameters (L eff , VT, VDD, and Wdoi:10.1109/isqed.2007.115 dblp:conf/isqed/MondalMM07 fatcat:6wxuf7vy7bcrretbtqtqidiyay