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Multi-frequency wrapper design and optimization for embedded cores under average power constraints
2005
Proceedings. 42nd Design Automation Conference, 2005.
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. We present an integer linear programming (ILP) model that can be used to minimize the testing time for small problem instances. We also present an efficient heuristic method that
doi:10.1109/dac.2005.193785
fatcat:ckx7tyhk5jerhdjo2ri2zcwthm