In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40 of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13m standard CMOS technology to be integrated into ASIC designs that require serial links.

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... transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions. Index Terms-Adaptive equalization, backplane transceiver, decision feedback equalization (DFE), SerDes, serial link. Vishnu Balan (S'95-M'96) received the B.S. degree in electronics and communications engineering from the Indian Institute of Technology, Madras, in 1995 and the M.S. degree in electrical engineering from