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The need for efficient implementation of simple crossbar schedulers has increased in the recent years due to the advent of on-chip interconnection networks that require low latency message delivery. The core function of any crossbar scheduler is arbitration that resolves conflicting requests for the same output. Since, the delay of the arbiters directly determine the operation speed of the scheduler, the design of faster arbiters is of paramount importance. In this paper, we present a newdoi:10.1109/iccd.2008.4751932 dblp:conf/iccd/DimitrakopoulosCG08 fatcat:ybskqlupener5fkwlbhxjhsnsu