Novel design of driver and ESD transistors with significantly reduced silicon area

Koen G Verhaege, Markus Mergens, Christian Russ, John Armer, Phillip Jozwiak
2002 Microelectronics and reliability  
EOS/ESD symposium 2001 This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and Electro Static Discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um2 Human Body Model (HBM) were demonstrated. Significant silicon area reduction was demonstrated in deep-sub micron CMOS, ranging from 0.35um down to 0.13um CMOS. This novel design solution
more » ... ows standard design flows and does not require any process modifications. K.G. Verhaege et al. Abstract -This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and Electro Static Discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um 2 Human Body Model (HBM) were demonstrated. Significant silicon area reduction was demonstrated in deep-sub micron CMOS, ranging from 0.35um down to 0.13um CMOS. This novel design solution follows standard design flows and does not require any process modifications.
doi:10.1016/s0026-2714(01)00237-2 fatcat:us3h6eidgrbhjp3tg4ngihr6x4