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EOS/ESD symposium 2001 This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and Electro Static Discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um2 Human Body Model (HBM) were demonstrated. Significant silicon area reduction was demonstrated in deep-sub micron CMOS, ranging from 0.35um down to 0.13um CMOS. This novel design solutiondoi:10.1016/s0026-2714(01)00237-2 fatcat:us3h6eidgrbhjp3tg4ngihr6x4