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DRAM-Based Statistics Counter Array Architecture With Performance Guarantee
2012
IEEE/ACM Transactions on Networking
The problem of efficiently maintaining a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g., 40 Gb/s) has received considerable research attention in recent years. This problem arises in a variety of router management and data streaming applications where large arrays of counters are used to track various network statistics and implement various counting sketches. It proves too costly to store such large counter arrays entirely in SRAM, while
doi:10.1109/tnet.2011.2171360
fatcat:gsra6al4pvc43fbgecc2tm4dii