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FPGA based soft processors are an attractive option for implementing embedded applications. As energy efficiency has become a key performance metric, techniques that can quickly and accurately obtain the energy performance of these soft processors are needed. While low-level simulation based on traditional FPGA design flow is too time consuming for obtaining such energy performance, we propose a methodology based on instruction level energy profiling. We first analyze the energy dissipation ofdoi:10.1109/socc.2004.1362437 dblp:conf/socc/OuP04 fatcat:ibso6lorzvdpzpjkf3f557t4ku