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Debugging of speed-limiting paths (speedpaths) is a key challenge in development of Very-Large-Scale Integrated (VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speedpaths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speedpaths. Thedoi:10.1109/ats.2012.42 dblp:conf/ats/DehbashiF12 fatcat:3yylfq272vfu7mg5wbhcirkjdm