Automated Post-Silicon Debugging of Failing Speedpaths

Mehdi Dehbashi, Gorschwin Fey
2012 2012 IEEE 21st Asian Test Symposium  
Debugging of speed-limiting paths (speedpaths) is a key challenge in development of Very-Large-Scale Integrated (VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speedpaths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speedpaths. The
more » ... mental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98.51% is achieved by our approach.
doi:10.1109/ats.2012.42 dblp:conf/ats/DehbashiF12 fatcat:3yylfq272vfu7mg5wbhcirkjdm