The paper presents a simulation-based test algorithm generation and test scheduling methodology for multi-port memories. The purpose is to minimize the testing time while keeping the test algorithm in a simple and regular format for easy test generation, fault diagnosis, and built-in self-test (BIST) circuit implementation. Conventional functional fault models are used to generate tests covering most defects. In addition, multi-port specific defects are covered using structural fault models.

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... t-scheduling is introduced to take advantage of the inherent parallelism among different ports. Experimental results for commonly used multi-port memories, including dual-port, four-port, and n-read-1-write memories, have been obtained, showing that efficient test algorithms can be generated and scheduled to meet different test bandwidth constraints. Moreover, memories with more ports benefit more with respect to testing time. Address α has a multiple access to Cell α and Cell β, so has port B Address β. The resulting value of a read to multiple cells depends on the memory design: possible faulty results are the logic-and or logic-or of the two cells. Note that Figure. 2 and 3 describe possible results because an inter-port short can lead to more than one faults on the same bit line or word line. Faulty Address 1 Port B Port A Figure 2: Functional behavior of an inter-port word line short.