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IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs
<span title="">2018</span>
<i title="IEEE">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/e6tknrargzacdbrlh7gyvin3gq" style="color: black;">2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)</a>
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FPGA devices have been used widely in many industrial domains, but only limitedly in secure and safety-critical applications, which have special requirements for the physical implementation, such as module isolation. This is partly due to limited functionality available with current FPGA vendors' tools and flows. To extend FPGA's appearance in secure and safetycritical applications, we propose an alternative flow for isolation design called the Isolated Partial Reconfiguration Design Flow
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<a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/mcsoc2018.2018.00018">doi:10.1109/mcsoc2018.2018.00018</a>
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... ) in this paper. Systems designed by the proposed IPRDF are not only fully isolated but also support partial reconfiguration of insulated modules. This allows building secure and dependable systems that can use partial reconfiguration to mitigate from single-event upsets (SEUs) and that are more tolerant to aging and device imperfections. Further, this also allows information assurance applications to benefit from hardware module isolation and run-time reconfigurability. Case studies on isolated Triple Modular Redundancy (TMR) and single-chip cryptographic (SCC) designs are presented to demonstrate capabilities and advantages of the proposed IPRDF methodology.
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