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Fully Parallel Architecture of QC-LDPC Decoder for IEEE 802.11n Application
2020
International journal of recent technology and engineering
A Low density parity check (LDPC) code, have become most accepted error correction code for efficient and reliable communication due to a good performance. The VLSI implementation of LDPC decoder is a big challenge. Iterative message passing decoding algorithms propose excellent error correction performance but a large decoding complexity for different code lengths and code rates. The LDPC codes decoder also faced many difficulties such as small chip areas , reduced interconnect complexities,
doi:10.35940/ijrte.a2314.059120
fatcat:b5okkkiatjcjfc7c52ayxca6z4