Fully Parallel Architecture of QC-LDPC Decoder for IEEE 802.11n Application

2020 International journal of recent technology and engineering  
A Low density parity check (LDPC) code, have become most accepted error correction code for efficient and reliable communication due to a good performance. The VLSI implementation of LDPC decoder is a big challenge. Iterative message passing decoding algorithms propose excellent error correction performance but a large decoding complexity for different code lengths and code rates. The LDPC codes decoder also faced many difficulties such as small chip areas , reduced interconnect complexities,
more » ... wer power dissipation. In this paper, the design of the of Quasi Cyclic(QC)LDPC decoder for the IEEE 802.11n standard with 1/2 code rate, 648coward length and sub-block size z =27 have been designed. Initially different iterative algorithms for LDPC decoding are discussed. The Fully parallel architecture of the LDPC decoder for IEEE 802.11n standard using Min Sum decoding algorithm (MSA)has been designed. Further, the design Quasi Cyclic(QC) LDPC decoder for IEEE 802.11n have been modified by using a Finite State Machine (FSM) to control the complete decoding process.
doi:10.35940/ijrte.a2314.059120 fatcat:b5okkkiatjcjfc7c52ayxca6z4