Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip
[chapter]
Om Prakash Gangwal, Andrei Rădulescu, Kees Goossens, Santiago González Pestana, Edwin Rijpkema
2005
Philips Research
As the complexity of Systems-on-Chip (SoC) is growing, meeting real-time requirements is becoming increasingly difficult. Predictability for computation, memory and communication components is needed to build real-time SoC. We focus on a predictable communication infrastructure called the AEthereal Network-on-Chip (NoC). The AEthereal NoC is a scalable communication infrastructure based on routers and network interfaces (NI). It provides two services: guaranteed throughput and latency (GT), and
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... best effort (BE). Using the GT service, one can derive guaranteed bounds on latency and throughput. To achieve guaranteed throughput, buffers in NI must be dimensioned to hide round-trip latency and rate difference between computation and communication IPs (Intellectual Property). With the BE service, throughput and latency bounds cannot be derived with guarantees. In this chapter, we describe an analytical method to compute latency, throughput and buffering requirements for the AEthereal NoC. We show the usefulness of the method by applying it on an MPEG-2 (Moving Picture Experts Group) codec example. Slave consumer producer NoC REQ RESP REQ RESP NI NI forward channel reverse channel Master producer consumer β F,M β F,S β R,S β R,M connection Figure 1-1. Connection example. are characterized by the fact that they produce/consume data periodically. Using this and the AEthereal NoC's guaranteed-throughput service, we show how to compute the latency and throughput for the worst-case. We also compute the lower-bound sizes of the buffers between the NoC and the IP modules that guarantee the latency and throughput requirements are met. All these computations have been implemented in a verification tool, which is used by the AEthereal design flow (Goossens, Dielissen, Gangwal, González Pestana, Rȃdulescu and Rijpkema, 2005; Goossens, González Pestana, Dielissen, Gangwal, van Meerbergen, Rȃdulescu, Rijpkema and Wielage, 2005) to dimension and configure the NoC to satisfy the application requirements. We illustrate the use of the verification tool by applying it to an MPEG-2 (Moving Pictures Expert Group) codec example. The chapter is organized as follows. In the next section, we describe the basics of the AEthereal NoC, focusing on the guaranteed-throughput and -latency communication services. In this section, we also define a communication model for the IP modules, and introduce some notation used in the chapter. In Section 3, we use these models to derive the throughput resulting from a given NoC for which the slots have been allocated. In Section 4, we compute the lower-bound sizes of the buffers between NoC and the IP modules. Further, in Section 5, we derive the latency that results from a given system consisting of a NoC and its attached IP modules. Our, throughput, buffer size, and latency formalizations and their implementation in a verification tool are shown in use by means of an MPEG-2 codec example in Section 6. We present our conclusions in Section 7. To ease reading, we also include in Section 8 a list of symbols used throughout the paper. AN ANALYTICALLY VERIFIABLE SoC MODEL In this section, we first describe the AEthereal NoC, focusing on the aspects that impact NoC analysis. Then, we list the conditions that IP modules need to satisfy to enable (sub)system analytical verification.
doi:10.1007/1-4020-3454-7_1
fatcat:oelt2x4ckbda7pdqdikubqntou