Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA

Vijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, Massood Tabib-Azar
2010 2010 International Conference on Field Programmable Logic and Applications  
Static power consumption has become a major concern in the design. To address this, we have designed a novel Nano-Electro-Mechanical (NEM) switch with virtually zero leakage current, 1 to 2 Volts operation voltage, 1 ns switching time, > 1 GHz fundamental resonant frequency, and nanometer-scale footprint. Positive and negative channel switches from Complementary NEMS (CNEMS), similar to CMOS. Due to compatibility between CNEMS and CMOS, these CNEMS switches can be hybridized with CMOS at the
more » ... allization or device. In this paper, we present the CNEMS design, its electrical properties and a hybrid FPGA with CNEM switches. We used VPR to simulate the MCNC benchmark circuits routed on our hybrid FPGA for power and delay. Our experimental results show an average 98%, 85%, 71% and 99.99% reduction in critical path delay, routing energy, total energy, leakage power when comparisons are made with FPGA design using pure CMOS technology (180 nm technology and hybrid CNEMS and 180 nm CMOS).
doi:10.1109/fpl.2010.79 dblp:conf/fpl/SirigirASKT10 fatcat:zgwuvp47srheho5a7ixqxvvcj4