A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is
As the impact of the communication architecture on performance grows in a Multiprocessor Systemon-Chip (MPSoC) design, the need for performance analysis in the early stage in order to consider various communication architectures is also increasing. While a simulation is commonly performed for performance evaluation of an MPSoC, it often suffers from a lengthy run time as well as poor performance coverage due to limited input stimuli or their ad hoc applications. In this paper, we propose adoi:10.1016/j.micpro.2014.02.003 fatcat:wsonxvepd5gfthhxp5ehlebrma