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HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
2005
International Workshop on Microprocessor Test and Verification
Today, the underlying hardware of embedded systems is often verified successfully. In this context formal verification techniques allow to prove the correctness. But in embedded system design the integration of software components becomes more and more important. In this paper we present an integrated approach for formal verification of hardware and software. The approach is demonstrated on a RISC CPU. The verification is based on bounded model checking. Besides correctness proofs of the
doi:10.1109/mtv.2005.12
dblp:conf/mtv/GrosseKD05
fatcat:yvg5jdtu3vds3f24vribe52rbu