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The synthesis of hardware from object oriented specifications is presented. Our approach utilizes the e language that has been proven to be highly efficient for the verification of hardware. The e language is similar to Java and provides additional constructs for specification and verification of hardware. We describe an automated design flow for the synthesis of object oriented descriptions that tightly integrates simulation based verification. The usability of our approach is demonstrated bydoi:10.1109/isss.2001.957937 dblp:conf/isss/KuhnOSWREK01 fatcat:vnouqwwgcfhsjlhpubv4gqd7je