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Mitigating the impact of faults in unreliable memories for error-resilient applications
2015
Proceedings of the 52nd Annual Design Automation Conference on - DAC '15
Inherently error-resilient applications in areas such as signal processing, machine learning and data analytics provide opportunities for relaxing reliability requirements, and thereby reducing the overhead incurred by conventional error correction schemes. In this paper, we exploit the tolerable imprecision of such applications by designing an energyefficient fault-mitigation scheme for unreliable data memories to meet target yield. The proposed approach uses a bit-shuffling mechanism to
doi:10.1145/2744769.2744871
dblp:conf/dac/GanapathyKTB15
fatcat:mwwngmb4pvfvhoh7bpynbncy6a